The present invention relates to semiconductor device techniques, and in particular, relates to a technique effectively applied to a SiP (System in Package), in which a first semiconductor chip including an amplifier and a second semiconductor chip including a control circuit for controlling the operation of this amplifier are mixedly mounted inside a single sealing body to configure a desired circuit function.
The SiP is an approach for configuring a desired circuit function inside a single sealing body by sealing a plurality of semiconductor chips inside the single sealing body. In the case of SiP, since already developed semiconductor chips can be directly applied, the development time can be reduced as compared with SOC (System On Chip) and furthermore the development cost can be suppressed. Moreover, in the case of SOC, wide variety of memories are difficult to be mixedly mounted inside a single semiconductor chip, while in the case of SiP, wide variety of large capacity memories can be mixedly mounted with ease. Moreover, in the case of SiP, the wiring length can be shortened as compared with the case where a plurality of packages is mounted on a wiring board to configure a desired circuit function, and it is therefore possible to promote higher speed and higher performance of the whole semiconductor device.
Such a SiP is described in Japanese Patent No. 2566207 (Patent Document 1), for example. Here, there is disclosed a structure, in which a semiconductor substrate including a power MOSFET and a semiconductor substrate including a control circuit for controlling the operation of this power MOSFET are stacked in this order from the lower layer over a cooling body. A sensor for detecting the temperature caused by the operation of the lower-side power MOSFET is arranged in the upper-side semiconductor substrate including the control circuit so that the power MOSFET may be turned off by the operation of this sensor.
Moreover, for example, Japanese Unexamined Patent Publication No. 2003-31736 (Patent Document 2) discloses a structure, in which the rear surface of a heat spreader mounting a semiconductor chip is exposed from a resin body.
Moreover, for example, Japanese Unexamined Patent Publication No. 11-163256 (Patent Document 3) discloses a structure, in which the rear surface side of either of two semiconductor chips stacked with their mutual major surfaces facing each other is exposed from a packaging resin.